As processors incorporate more computing cores, either heterogeneous or homogeneous, and computer systems incorporate more processors, management of interrupts becomes increasingly difficult. Some prior art techniques have managed interrupts using a memory-mapped-input/output (MMIO) scheme, in which a processor or core (referred to generically herein as “agent”) communicates interrupt information through a region of memory (e.g., DRAM) specifically reserved for interrupt communication information. For example, one prior art interrupt communicating technique, in which an advanced programmable interrupt controller (APIC) is to be programmed, may communicate the information to be programmed to the APIC through the MMIO region.
Communication of interrupt information to/from an APIC in through MMIO may have several drawbacks, which are exacerbated as the number of agents, and therefore interrupt traffic, increases. For example, MMIO accesses may require the memory region associated with the APIC to be mapped with an un-cached (UC) access attribute, which has a high performance overhead associated with it. The UC interface also enforces a serialization behavior, which may not be needed for a large subset of the APIC registers.
Using an MMIO interface may also require the use of posted write semantics and provides an agent with limited control over ordering of reads and writes to the APIC, which can impact the efficiency of sending interrupts with a larger number of reads/writes needed for basic interrupt related instructions. For example, sending an interrupt from one processor to another via inter-processor interrupt (IPI) in some prior art MMIO implementations, may require either 1 UC read and 2 UC writes if software does not need a guarantee that the interrupt has left the local APIC or 2 UC reads and 2 UC writes if software needs a guarantee that the interrupt has left the local APIC.
Use of a prior art MMIO interface may limit the ability to efficiently provide the system software desired mechanisms for interrupt delivery. Specific examples include operations for changing interrupt priority levels, which may be done in some prior art implementations by system software writing to the task priority register (TPR), and “end-of-interrupt” (EOI) operations, which may be done by system software writing to the EOI register of the APIC. System software may desire completion of these operations to be associated with completion of any re-prioritization operation so that any interrupts deterministically posted ahead of these operations are raised immediately following these operations. Lacking these guarantees, system software may use inefficient polling-based mechanisms, which increase APIC traffic.
Use of MMIO-based interrupt information may also affect other features within a computer system. For example, use of prior art MMIO interrupt communication interface techniques may increases virtualization complexity and overhead for virtualization of APIC accesses. For example, instructions that are used to access the interrupt controller may require the use of a virtual machine monitor (VMM) to support virtualization in a computer system. The overhead previously discussed with MMIO operations may be compounded with those used by the VMM to enter and exit virtual machines in the system.
Lastly, detecting and enforcing reserved bits within an APIC interface may have a high implementation cost when interfaced through MMIO, particularly as the number of agents using the APIC is increased. Some prior art interrupt communication techniques may limit the use of reserved bit locations for future extendable architectures since legacy software could incorrectly write to one of the registers.
For at least the above reasons, some prior art interrupt communication techniques, including those that use MMIO in communicating interrupt information, may not be suitable to support an increasing number of processing cores in multi-core processors or processors in multiprocessor systems.